1. Field of the Invention
This invention is related in general to the field of electronic microscopes and cameras for testing integrated circuits in wafer or chip form. In particular, the invention concerns the use of an infrared microscope for imaging and aligning the probe tips of a conventional probe card with the electrical contact pads of the integrated circuit. It also enables more advanced probe cards to be used with flip-chip technology.
2. Description of the Related Art
Conventional testing of integrated circuits (ICs) is carried out on an individual IC at the wafer level by contacting the electrical contact pads of the IC with the finger tips of a probe card facing the top side of the circuit. The probe card energizes the circuit and performs diagnostic tests that enable the detection of faults, which may then be specifically identified with further testing performed on individually mounted chips. For example, recent advances in the art have been obtained by using an infrared (IR) microscope to image hot-carrier emission and black-body radiation caused by circuit failures. These failures can be viewed directly by imaging the integrated circuit with light of infrared wavelength. See, for example, Steve Seidel et al., xe2x80x9cApplication of Infrared Emission Microscope for Flip-Chip (C4) Failure Analysis,xe2x80x9d Conf. Proc. for 25th ISTFA, November 1999, pp. 471-476. Thus, the full power of IR microscopy has been limited to packaged parts.
During the process of establishing the electrical contacts required for testing of a chip, the tips of the probe card must first be aligned vertically over the contact pads of the integrated circuit, and then the probe tips are lowered and pressed against the pads to establish contact. In order to implement the initial alignment, conventional equipment utilizes a visible-light camera adapted to view the pads and probe tips through a top-side viewing port in the probe card; contact between corresponding probe tips and IC pads is then ensured by overcoming with sufficient downward pressure any horizontal misalignment resulting from a tip or tilt of the probe card with respect to the underlying chip.
Several disadvantages characterize this prior-art approach. As one skilled in the art would readily recognize, the tips of the contact fingers of a probe card are curved vertically downward after an initial radial extension inward from the edge of the viewing port; thus, the tips are not all clearly visible to an imaging device placed substantially vertically above the viewing port. Therefore, the vertical alignment of the probe tips with the IC contact pads is not as precise as it would be if the tips were imaged in their entirety. In addition, current top-side imaging is limited to contact pads that are positioned at the edges of the integrated circuit in order to provide room for the viewing port through the probe card. Thus, recently introduced xe2x80x9cflip-chipxe2x80x9d probe cards, which have probe tips designed to match contact pads located throughout the interior of the chip, cannot be aligned with conventional top-side imaging.
The relative lack of access to a clear view of all probe tips afforded by the prior art also prevents a determination of their precise spatial position and an adjustment of their planar attitude with respect to the plane of the IC contact pads. As a result, the electrical contact between all probe-pad pairs is ensured only by lowering the probe card a sufficient distance to cause the union of even the most distant pairs. Obviously, any such horizontal misalignment (that is, lack of parallelism) between the planes of the probe tips and the IC contact pads causes an uneven distribution of the downward force exerted by the probe card on the IC substrate, which may adversely affect the proper performance of the circuit. Most importantly, though, the pressure required to overcome such misalignments may cause the circuit""s silicon substrate to bend and possibly be damaged. In the case of thinned wafers that are not properly supported, these excess forces can break the wafer.
In view of these shortcomings of current IC testing apparatus and procedures, there is still a need for a device that permits the precise, relatively stress-free, alignment of all types of probe cards, including flip-chip cards with more rigid probe tips, with integrated circuits in wafer form. The present invention is based on back-side imaging of the integrated circuit and the probe tips with an infrared microscopic device capable of viewing both from the bottom of the IC silicon substrate. Since packaged parts will suffer additional failures, the apparatus must retain its ability to mount and analyze packaged parts.
The primary objective of this invention is a fast and precise system for aligning the contact pads of an integrated circuit with corresponding probe tips in a probe card, regardless of the position of the pads within the circuit and of access from the top side of the card.
Another goal of this invention is a device and an associated procedure that provide adequate support of the wafer while providing a viewing window large enough to image the IC under test.
Another goal of the invention is a device and an associated procedure that minimizes the pressure exerted by the probe tips over the integrated circuit, so as to avoid bending of its substrate and any damage that may otherwise result from structural stresses.
Another objective is an apparatus suitable for carrying out both the alignment of the integrated circuit with the probe card and the normal testing of the circuit in a single operation.
Another object is an apparatus suitable for testing integrated circuits both in the form of a packaged chip and in the form of a wafer.
Still another object is an approach suitable for automated implementation, so that multiple tests can be carried out with speed and reliability for quality control of several integrated circuits in a water.
Another goal is also a method and apparatus that are suitable for incorporation within existing instruments.
A final objective is a system that can be implemented easily and economically according to the above stated criteria.
Therefore, according to these and other objectives, the preferred is embodiment of the present invention includes a back-side imaging infrared microscope combined with a conventional integrated-circuit probe card mounted on a platen that lowers the probe card to make contact with the top side of the wafer. At the same time, the microscope is located below the silicon substrate of the integrated circuit, on the side opposite to the probe card. The back side of the substrate is imaged through a window sized to provide a view of a single integrated circuit and of the corresponding probe tips overlying the contact pads, while also providing sufficient vertical support to minimize bending of the silicon substrate. Since the silicon substrate of integrated circuits is transparent to infrared wavelengths, the alignment between probe tips and contact pads can be carried out with a clear view of both from the bottom of the substrate. Appropriate mechanisms for angular and x,y,z position adjustments of the probe card with respect to the integrated circuit enable their vertical and parallel alignment. Furthermore, emission images from the integrated circuit can be taken during testing with the same microscope after electrical contact has been established. By using a single microscope for testing and alignment from the bottom side of the silicon substrate, precise alignment becomes possible even when the entire top side of the circuit is dedicated to accommodate electrical contacts.
According to another aspect of the invention, a special supporting plate with a bottom view window is combined with a movable frame for an IC wafer. The frame is adapted for slidable, precisely controlled motion over the supporting plate, so that multiple circuits in a wafer can be positioned sequentially over the view window, aligned with the probe card, and tested by imaging infrared emissions caused by circuit failures. Thus, the full benefits of IR microscopy can be applied to integrated circuits before they are packaged. Initial detection of a fault and the subsequent failure analysis, which have been so far performed in two separate steps, are combined into a single operation by the present invention.
Various other purposes and advantages of the invention will become clear from its description in the specification that follows and from the novel features particularly pointed out in the appended claims. Therefore, to the accomplishment of the objectives described above, this invention consists of the features hereinafter illustrated in the drawings, fully described in the detailed description of the preferred embodiment and particularly pointed out in the claims. However, such drawings and description disclose but one of the various ways in which the invention may be practiced.